1. Field of the Invention
Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors in complex circuits, wherein transistor performance is increased by producing strain in the channel region on the basis of a dielectric layer comprising a high intrinsic stress.
2. Description of the Related Art
Integrated circuits are manufactured by forming a large number of circuit elements on a given chip area on the basis of complex microelectronic techniques including, for example, lithography, etching, deposition and implantation techniques. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as micro-processors, storage chips and the like, CMOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers, and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions also raises a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is the reduction of so-called short channel effects, which occur upon reducing the channel length. Generally, with a reduced channel length, the controllability of the channel becomes increasingly difficult and requires specific design measures, such as reduction of the thickness of the gate insulation layer, increased doping concentrations in the channel regions and the like. Some of these countermeasures may, however, reduce the charge carrier mobility in the channel region, thereby reducing transistor performance. Accordingly, to compensate or even overcompensate for these effects, it has been proposed to increase the charge carrier mobility in the channel region for a given channel length.
In principle, at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region. First, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device and may affect the channel controllability as previously explained, thereby making a reduction of the dopant concentration a less attractive approach unless other mechanisms are developed so as to adjust a desired threshold voltage. Second, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region along a standard crystallographic orientation may increase the mobility of electrons, which, in turn, may directly translate into a corresponding increase in the conductivity for N-type transistors. On the other hand, compressive strain in the channel region along the channel length direction may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
Therefore, a technique is frequently used that enables the creation of desired stress conditions within the channel region of different transistor elements by individually modifying the stress characteristics of a contact etch stop layer that is formed after completion of the basic transistor structure in order to form contact openings in an interlayer dielectric material for connecting to the gate and drain and source terminals. The effective control of mechanical strain in the channel region, i.e., effective stress or strain engineering, may be accomplished by individually adjusting the internal stress in the contact etch stop layers in order to position a contact etch contact layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile stress above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used, due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 2 Giga Pascal (GPa) or significantly higher of compressive stress and up to 2 GPa of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas components and the like represent respective parameters that may be used for obtaining the desired intrinsic stress. Since the contact etch stop layer is positioned close to the transistor, the intrinsic stress may be efficiently transferred into the channel region, thereby significantly improving the performance thereof. Moreover, for advanced applications, the strain-inducing contact etch stop layer may be efficiently combined with other strain-inducing mechanisms, such as strained or relaxed semiconductor materials that are incorporated at appropriate transistor areas in order to also create a desired strain in the channel region. Consequently, the stressed contact etch stop layer is a well-established design feature for advanced semiconductor devices, wherein, however, the interaction of the contact etch stop layer with the overlying interlayer dielectric material, i.e., silicon dioxide formed from TEOS on the basis of PECVD due to the advantageous characteristics with respect to material integrity in the further manufacturing process, may result in a reduced performance gain. Thus, it has been proposed to increase the thickness of the stressed contact etch stop layer in order to enhance the strain in the channel regions. However, the device topography of advanced field effect transistors may impose severe restrictions for depositing the stressed silicon nitride material. For example, the gate height may represent one limitation for continuously increasing the strain, since the significant amounts of stressed material above the gate electrode may negatively influence the strain transfer mechanism. Simply increasing the gate height may, however, be a less desirable solution to this problem, since the patterning process for advanced transistors is highly complex and may therefore lead to additional process issues. Moreover, the corresponding fringing capacitance of the gate electrodes may also increase with an increasing gate height, thereby reducing the device performance. Furthermore, for a given distance between closely spaced gate electrodes, the fill capability of the deposition process may result in corresponding voids in the stressed silicon nitride material, thereby resulting in respective process nonuniformities during the subsequent contact etch process, when contact openings have to formed in the dielectric material enclosing the transistors.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.